An Intrinsically Robust Technique for Fault Tolerance Under Multiple Upsets

Future technologies below 90nm will present transistors so small that they will be heavily influenced by electromagnetic noise and SEU induced errors. This way, together with process variability, design as known today is likely to change. Since many soft errors might appear at the same time, a different design approach must be taken. The use of stochastic computation operators as an inherently robust alternative to conventional digital arithmetic operators is proposed in this study. The behavior of stochastic multipliers and adders is analyzed through the simulation of single and multiple random faults injection, and it is shown to be adequate for several classes of applications. The space-time tradeoffs are commented and future research to be conducted to further develop and enhance the concepts herein introduced is described.